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Lane-Based Hardware Specialization for Loop-and Fork-Join-Centric Parallelization and Scheduling Strategies
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| 자료유형 | E-Book |
|---|---|
| 개인저자 | Srinath, Shreesha. |
| 단체저자명 | Cornell University. Electrical & Computer Engineering. |
| 서명/저자사항 | Lane-Based Hardware Specialization for Loop-and Fork-Join-Centric Parallelization and Scheduling Strategies. |
| 발행사항 | [S.l.] : Cornell University., 2018 |
| 발행사항 | Ann Arbor : ProQuest Dissertations & Theses, 2018 |
| 형태사항 | 145 p. |
| 소장본 주기 | School code: 0058. |
| ISBN | 9780438342057 |
| 일반주기 |
Source: Dissertation Abstracts International, Volume: 80-01(E), Section: B.
Adviser: Christopher Batten. |
| 요약 | Serious physical design issues are breaking down traditional abstractions in computer architec- ture. For the past 40 years, Moore's Law and Dennard's Scaling have provided the smaller, cheaper, faster, and more power-efficient transistors that |
| 요약 | In this thesis, I present a lane-based hardware specialization approach to building programmable accelerators for loop- and fork-join-centric parallel programs. To mitigate the design costs and in- crease the applicability of hardware specializa |
| 일반주제명 | Computer engineering. Engineering. |
| 언어 | 영어 |
| 기본자료 저록 | Dissertation Abstracts International80-01B(E). Dissertation Abstract International |
| 대출바로가기 | http://www.riss.kr/pdu/ddodLink.do?id=T14999381 |
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| No. | 등록번호 | 청구기호 | 소장처 | 도서상태 | 반납예정일 | 예약 | 서비스 | 매체정보 |
|---|---|---|---|---|---|---|---|---|
| 1 | WE00028019 | 621.3 | 가야대학교/전자책서버(컴퓨터서버)/ | 대출가능 |
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