| LDR | | 01838nmm uu200409 4500 |
| 001 | | 000000333692 |
| 005 | | 20240805173525 |
| 008 | | 181129s2018 |||||||||||||||||c||eng d |
| 020 | |
▼a 9780438342057 |
| 035 | |
▼a (MiAaPQ)AAI10830022 |
| 035 | |
▼a (MiAaPQ)cornellgrad:10906 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 248032 |
| 082 | 0 |
▼a 621.3 |
| 100 | 1 |
▼a Srinath, Shreesha. |
| 245 | 10 |
▼a Lane-Based Hardware Specialization for Loop-and Fork-Join-Centric Parallelization and Scheduling Strategies. |
| 260 | |
▼a [S.l.] :
▼b Cornell University.,
▼c 2018 |
| 260 | 1 |
▼a Ann Arbor :
▼b ProQuest Dissertations & Theses,
▼c 2018 |
| 300 | |
▼a 145 p. |
| 500 | |
▼a Source: Dissertation Abstracts International, Volume: 80-01(E), Section: B. |
| 500 | |
▼a Adviser: Christopher Batten. |
| 502 | 1 |
▼a Thesis (Ph.D.)--Cornell University, 2018. |
| 520 | |
▼a Serious physical design issues are breaking down traditional abstractions in computer architec- ture. For the past 40 years, Moore's Law and Dennard's Scaling have provided the smaller, cheaper, faster, and more power-efficient transistors that |
| 520 | |
▼a In this thesis, I present a lane-based hardware specialization approach to building programmable accelerators for loop- and fork-join-centric parallel programs. To mitigate the design costs and in- crease the applicability of hardware specializa |
| 590 | |
▼a School code: 0058. |
| 650 | 4 |
▼a Computer engineering. |
| 650 | 4 |
▼a Engineering. |
| 690 | |
▼a 0464 |
| 690 | |
▼a 0537 |
| 710 | 20 |
▼a Cornell University.
▼b Electrical & Computer Engineering. |
| 773 | 0 |
▼t Dissertation Abstracts International
▼g 80-01B(E). |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0058 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2018 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T14999381
▼n KERIS |
| 980 | |
▼a 201812
▼f 2019 |
| 990 | |
▼a 관리자 |