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Improved Timing Error Resilience of Microelectronic Computing Systems using Cross-layer Optimizations
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| 자료유형 | E-Book |
|---|---|
| 개인저자 | Jiao, Xun. |
| 단체저자명 | University of California, San Diego. Computer Science. |
| 서명/저자사항 | Improved Timing Error Resilience of Microelectronic Computing Systems using Cross-layer Optimizations. |
| 발행사항 | [S.l.] : University of California, San Diego., 2018 |
| 발행사항 | Ann Arbor : ProQuest Dissertations & Theses, 2018 |
| 형태사항 | 120 p. |
| 소장본 주기 | School code: 0033. |
| ISBN | 9780438168602 |
| 일반주기 |
Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B.
Adviser: Rajesh Gupta. |
| 요약 | Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance advantages that continue to drive new devices and systems from high-performance computing to ultra-low power Internet endpoints. This scaling, ho |
| 요약 | This dissertation focuses on methods to improve the timing error resilience of microelectronic computing systems by reducing the guardbands which also results in improved operational efficiency if microelectronic circuits. Timing errors can show |
| 일반주제명 | Computer engineering. |
| 언어 | 영어 |
| 기본자료 저록 | Dissertation Abstracts International79-12B(E). Dissertation Abstract International |
| 대출바로가기 | http://www.riss.kr/pdu/ddodLink.do?id=T14998528 |
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| No. | 등록번호 | 청구기호 | 소장처 | 도서상태 | 반납예정일 | 예약 | 서비스 | 매체정보 |
|---|---|---|---|---|---|---|---|---|
| 1 | WE00024102 | 621.3 | 가야대학교// | 대출가능 |
|
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