| LDR | | 00000nmm u2200205 4500 |
| 001 | | 000000329775 |
| 005 | | 20241016151318 |
| 008 | | 181129s2018 ||| | | | eng d |
| 020 | |
▼a 9780438168602 |
| 035 | |
▼a (MiAaPQ)AAI10822969 |
| 035 | |
▼a (MiAaPQ)ucsd:17450 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 248032 |
| 049 | 1 |
▼f DP |
| 082 | 0 |
▼a 621.3 |
| 100 | 1 |
▼a Jiao, Xun. |
| 245 | 10 |
▼a Improved Timing Error Resilience of Microelectronic Computing Systems using Cross-layer Optimizations. |
| 260 | |
▼a [S.l.] :
▼b University of California, San Diego.,
▼c 2018 |
| 260 | 1 |
▼a Ann Arbor :
▼b ProQuest Dissertations & Theses,
▼c 2018 |
| 300 | |
▼a 120 p. |
| 500 | |
▼a Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B. |
| 500 | |
▼a Adviser: Rajesh Gupta. |
| 502 | 1 |
▼a Thesis (Ph.D.)--University of California, San Diego, 2018. |
| 520 | |
▼a Microelectronic scaling has entered into the nanoscale era with tremendous capacity and performance advantages that continue to drive new devices and systems from high-performance computing to ultra-low power Internet endpoints. This scaling, ho |
| 520 | |
▼a This dissertation focuses on methods to improve the timing error resilience of microelectronic computing systems by reducing the guardbands which also results in improved operational efficiency if microelectronic circuits. Timing errors can show |
| 590 | |
▼a School code: 0033. |
| 650 | 4 |
▼a Computer engineering. |
| 690 | |
▼a 0464 |
| 710 | 20 |
▼a University of California, San Diego.
▼b Computer Science. |
| 773 | 0 |
▼t Dissertation Abstracts International
▼g 79-12B(E). |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0033 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2018 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T14998528
▼n KERIS |
| 980 | |
▼a 201812
▼f 2019 |
| 990 | |
▼a 관리자
▼b 관리자 |