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020 ▼a 9780438027244
035 ▼a (MiAaPQ)AAI10817347
035 ▼a (MiAaPQ)cornellgrad:10858
040 ▼a MiAaPQ ▼c MiAaPQ ▼d 248032
0820 ▼a 621.3
1001 ▼a Ferraiuolo, Andrew.
24510 ▼a Timing-Safe Hardware-Level Information Flow Control.
260 ▼a [S.l.] : ▼b Cornell University., ▼c 2018
260 1 ▼a Ann Arbor : ▼b ProQuest Dissertations & Theses, ▼c 2018
300 ▼a 234 p.
500 ▼a Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B.
500 ▼a Adviser: Edward Suh.
5021 ▼a Thesis (Ph.D.)--Cornell University, 2018.
520 ▼a Developing secure processors has become increasingly important. Recent advancements in commercial security architectures such as Intel SGX have garnered much attention. The promise of these architectures is compelling
520 ▼a Information flow security is a promising approach for verifying hardware systems. Information flow tracks and constrains the movement of data throughout a system ensuring that confidentiality and integrity are not violated. Information flow cont
520 ▼a This thesis enables future hardware designs to provide strong assurance through information flow control. This is achieved through two major thrusts of research: 1) developing a practical, expressive hardware description language for enforcing i
590 ▼a School code: 0058.
650 4 ▼a Computer engineering.
650 4 ▼a Computer science.
690 ▼a 0464
690 ▼a 0984
71020 ▼a Cornell University. ▼b Electrical and Computer Engineering.
7730 ▼t Dissertation Abstracts International ▼g 79-10B(E).
773 ▼t Dissertation Abstract International
790 ▼a 0058
791 ▼a Ph.D.
792 ▼a 2018
793 ▼a English
85640 ▼u http://www.riss.kr/pdu/ddodLink.do?id=T14998352 ▼n KERIS
980 ▼a 201812 ▼f 2019
990 ▼a 관리자