LDR | | 00000nmm u2200205 4500 |
001 | | 000000332292 |
005 | | 20241127172814 |
008 | | 181129s2018 ||| | | | eng d |
020 | |
▼a 9780438017320 |
035 | |
▼a (MiAaPQ)AAI10751825 |
035 | |
▼a (MiAaPQ)purdue:22409 |
040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 248032 |
049 | 1 |
▼f DP |
082 | 0 |
▼a 621.3 |
100 | 1 |
▼a Sharma, Ankit. |
245 | 10 |
▼a Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs. |
260 | |
▼a [S.l.] :
▼b Purdue University.,
▼c 2018 |
260 | 1 |
▼a Ann Arbor :
▼b ProQuest Dissertations & Theses,
▼c 2018 |
300 | |
▼a 136 p. |
500 | |
▼a Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B. |
500 | |
▼a Adviser: Kaushik Roy. |
502 | 1 |
▼a Thesis (Ph.D.)--Purdue University, 2018. |
520 | |
▼a One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall en |
520 | |
▼a Using full band quantum mechanical model within the Non-Equilibrium Green's Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy so |
520 | |
▼a The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, an |
590 | |
▼a School code: 0183. |
650 | 4 |
▼a Electrical engineering. |
690 | |
▼a 0544 |
710 | 20 |
▼a Purdue University.
▼b Electrical and Computer Engineering. |
773 | 0 |
▼t Dissertation Abstracts International
▼g 79-10B(E). |
773 | |
▼t Dissertation Abstract International |
790 | |
▼a 0183 |
791 | |
▼a Ph.D. |
792 | |
▼a 2018 |
793 | |
▼a English |
856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T14997199
▼n KERIS |
980 | |
▼a 201812
▼f 2019 |
990 | |
▼a 관리자
▼b 관리자 |