| LDR | | 00000nmm u2200205 4500 |
| 001 | | 000000332007 |
| 005 | | 20241125162655 |
| 008 | | 181129s2018 ||| | | | eng d |
| 020 | |
▼a 9780438029507 |
| 035 | |
▼a (MiAaPQ)AAI10826681 |
| 035 | |
▼a (MiAaPQ)ucla:16867 |
| 040 | |
▼a MiAaPQ
▼c MiAaPQ
▼d 248032 |
| 049 | 1 |
▼f DP |
| 082 | 0 |
▼a 621.3 |
| 100 | 1 |
▼a Wang, Xiao. |
| 245 | 10 |
▼a Efficient Track-and-Hold Techniques for High Speed Time-interleaved ADCs. |
| 260 | |
▼a [S.l.] :
▼b University of California, Los Angeles.,
▼c 2018 |
| 260 | 1 |
▼a Ann Arbor :
▼b ProQuest Dissertations & Theses,
▼c 2018 |
| 300 | |
▼a 94 p. |
| 500 | |
▼a Source: Dissertation Abstracts International, Volume: 79-10(E), Section: B. |
| 500 | |
▼a Adviser: Mau-Chung Frank Chang. |
| 502 | 1 |
▼a Thesis (Ph.D.)--University of California, Los Angeles, 2018. |
| 520 | |
▼a Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H |
| 520 | |
▼a Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and bu |
| 590 | |
▼a School code: 0031. |
| 650 | 4 |
▼a Electrical engineering. |
| 690 | |
▼a 0544 |
| 710 | 20 |
▼a University of California, Los Angeles.
▼b Electrical Engineering 0303. |
| 773 | 0 |
▼t Dissertation Abstracts International
▼g 79-10B(E). |
| 773 | |
▼t Dissertation Abstract International |
| 790 | |
▼a 0031 |
| 791 | |
▼a Ph.D. |
| 792 | |
▼a 2018 |
| 793 | |
▼a English |
| 856 | 40 |
▼u http://www.riss.kr/pdu/ddodLink.do?id=T14998925
▼n KERIS |
| 980 | |
▼a 201812
▼f 2019 |
| 990 | |
▼a 관리자
▼b 관리자 |