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020 ▼a 9780438166943
035 ▼a (MiAaPQ)AAI10906700
040 ▼a MiAaPQ ▼c MiAaPQ ▼d 248032
0820 ▼a 621.3
1001 ▼a Sadi, Mehdi.
24510 ▼a On-Chip Structures for Reliability Management of System-on-Chips.
260 ▼a [S.l.] : ▼b University of Florida., ▼c 2017
260 1 ▼a Ann Arbor : ▼b ProQuest Dissertations & Theses, ▼c 2017
300 ▼a 130 p.
500 ▼a Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B.
5021 ▼a Thesis (Ph.D.)--University of Florida, 2017.
520 ▼a With aggressive technology scaling in the finfet era the transistor density per unit chip area has increased significantly over the past decade. As a result billion transistor complex System on Chips (SoC) that integrate multicore processors, me
520 ▼a Increased functional density with shrinking technology could result in escalating PSN induced failures in the field. To address these issues, a fully digital on-chip distributed sensor network is presented to continuously monitor the PSN profile
520 ▼a Because of process variation induced device and interconnect parametric shifts, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. As a result the operating speed or FMAX varies from sample t
520 ▼a In this paper, a novel framework is presented for designing lifetime-reliable SoCs with self-adaptation capability against aging induced degradation. The proposed flow utilizes the existing Logic Built In Self Test (LBIST) hardware, and software
590 ▼a School code: 0070.
650 4 ▼a Computer engineering.
650 4 ▼a Electrical engineering.
690 ▼a 0464
690 ▼a 0544
71020 ▼a University of Florida. ▼b Electrical and Computer Engineering.
7730 ▼t Dissertation Abstracts International ▼g 79-12B(E).
773 ▼t Dissertation Abstract International
790 ▼a 0070
791 ▼a Ph.D.
792 ▼a 2017
793 ▼a English
85640 ▼u http://www.riss.kr/pdu/ddodLink.do?id=T15000787 ▼n KERIS
980 ▼a 201812 ▼f 2019
990 ▼a 관리자