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Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems /
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| 자료유형 | E-Book |
|---|---|
| 개인저자 | Rhee, Woogeun, 1968-, editor. |
| 서명/저자사항 | Phase-locked frequency generation and clocking :architectures and circuits for modern wireless and wireline systems /edited by Woogeun Rhee. |
| 발행사항 | London, UK : The Institution of Engineering and Technology, 2020. |
| 형태사항 | 1 online resource (xvii, 715 pages) : illustrations |
| 총서사항 | IET materials, circuits and devices series ;64 |
| Architectures and circuits for modern wireless and wireline systems | |
| 소장본 주기 | Master record variable field(s) change: 050, 082 |
| ISBN | 9781785618864 1785618865 |
| 서지주기 | Includes bibliographical references and index (pages 697-715). |
| 내용주기 | Evolution of monolithic phase-locked loops / Woogeun Rhee -- Fractional-N frequency synthesis / Sudharkar Pamarti -- Clock data recovery : a system perspective / Fulvio Spagna -- Silicon-based THz frequency synthesizers with wide locking range / Payam Heydari -- Time-to-digital converters / Fa Foster Dai and Hechen Wang -- Bang bang digital PLLs for wireless systems / Salvatore Levantino and Carolo Samori -- Hybrid PLLs / Mark Ferriss and Daniel Friedman -- Spur mitigation techniques for DPLL architecture / Cheng-Ru Ho and Mike Shuo-Wei Chen -- Fully synthesized digital PLL / Bangan Liu, Wei Deng, and Kenichi Okada -- Ultra-low power ADPLL / Hanli Liu and Kenichi Okada -- Integrated LC oscillators / Jun Li and Yiwu Tang -- Mm-wave and sub-THz CMOS VCOs / Xiaolong Liu and Howard C. Luong -- Ultra-low phase noise ADPLL for millimeter wave / Zhirui Zong and Robert Bogdan Staszewski -- DTC-based subsampling PLLs for low-noise synthesis and two-point modulation / Nereo Markulic, Jan Craninckx and Piet Wambacq -- Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering / Ni Xu -- An overview of CDR in ultra-high-speed wireline transceivers / Jay Im and Hongtao Zhang -- Clock and data recovery for optical links / Wei Zen Chen, Ming-Chiuan Su, and Yuan-Sheng Lee -- Digital clock and data recovery circuits / Saurabh Saxena and Pavan Kumar Hanumolu -- Spread spectrum clock generator : a low-cost EMI solution / Minyoung Song and Chulwoo Kim -- High-performance CMOS clock distribution / Xunjun Mo, Nijwm Wary and Tony Chan Carusone -- Sub-sampling PLL techniques / Xiang Gao, Eric Klumperink and Bram Nauta -- PLLs with nested frequency-locked loop / Taekwang Jang, Dong-in Kim and SeongHwan Cho -- Time amplified charge pump PLL / Ping-Ying Wang -- Multiplying DLLs / Shiheng Yang, Jun Yin, Pui-In Mak and Rui P. Martins -- Widespread PLLs / Long Kong and Behzad Razavi. |
| 요약 | The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs. |
| 일반주제명 | Phase-locked loops. Phase-locked loops charge pump circuits. clock and data recovery circuits. clock distribution networks. clocks. CMOS digital integrated circuits. digital phase locked loops. direct digital synthesis. electromagnetic interference. elemental semiconductors. field effect MIMIC. field effect MMIC. FIR filters. frequency locked loops. frequency modulation. LC circuits. low-power electronics. millimetre wave oscillators. MMIC oscillators. multiplying circuits. optical links. phase locked oscillators. phase noise. silicon. submillimetre wave integrated circuits. submillimetre wave oscillators. time-digital conversion. transceivers. voltage-controlled oscillators. |
| 언어 | 영어 |
| 기타형태 저록 | Print version:Phase-locked frequency generation and clocking.[S.l.] : INST OF ENGIN AND TECH, 20201785618857 |
| 대출바로가기 | http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=2449704 |
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